1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly, to a cache memory used in all levels of computers, such as a super computer, a large size computer, a work station, and a personal computer, in order to increase the operation speed, and in particularly, to shorten a read time or write time of a memory.
2. Description of the Background Art
FIG. 5 is a block diagram showing a logical configuration of a conventional cache memory, which is a direct map configuration having the number of ways reduced from 2 to 1 for description of a cache memory of VAX-11/780 introduced in FIG. 8. 11 of "COMPUTER ARCHITECTURE A QUANTITATIVE APPROACH" written by John L. Hennessy and David A. Patterson, published from Morgan Kaufmann Publishers Inc., for example.
Referring to FIG. 5, the cache memory includes a static memory region 1 and a comparison logic circuit 7. Memory region 1 includes a plurality of (for example, 512) entries 2. Each entry 2 includes a data memory region 3 storing data (for example, 64 bits) of a main memory device, not shown, a tag memory region 4 storing upper bits (for example, 20 bits, which is referred to as tag data) of an address of the data stored in data memory region 3 in the main memory device, and a status valid bit region 5 storing status valid data (for example, one bit) indicating whether or not data stored in data memory region 3 and tag memory region 4 are valid or not.
On the other hand, an address bit train 10 externally applied to the cache memory includes an uppermost tag portion 11 (20 bits in this case), an intermediate index portion 12 (nine bits in this case) and a lowermost block offset portion 13 (for example, three bits) corresponding to the cache memory configuration. Data to be accessed is uniquely positioned by index portion 12. In other words, 9-bit index portion 12 corresponds to 512 entries 2.
Upon external application of address bit train 10, a bit train of index portion 12 included therein is decoded, and one of 512 entries 2 is selected. Then, data of data memory region 3, tag data of tag memory region 4, and status valid data of status valid bit region 5, of selected entry 2 are read out. Comparison logic circuit 7 compares the read tag data with a tag portion 11 of address bit train 10. When the tag data and tag portion 11 match, and the read status valid data is valid, comparison logic circuit 7 provides a hit signal HIT outside, and indicates that the data provided outside is correct. When the read status valid data is invalid, comparison logic circuit 7 provides a miss signal MISS outside, and indicates that the data provided outside is invalid.
Memory region 1 of the cache memory shown in FIG. 5 is actually configured of a plurality of memory cell arrays 14 disposed in the Y direction as shown in FIG. 7. FIG. 6 is a block diagram showing a specific configuration of one memory cell array 14. Referring to FIG. 6, memory cell array 14 includes a plurality of static memory cells 15 disposed in a matrix in X and Y directions, a plurality of word lines 16 connected to memory cell rows 15x (each including a plurality of static memory cells 15 disposed in line in the X direction), a word line peripheral circuit 17 including a row decoder and the like, a plurality of bit line pairs 18, 18 each connected to memory cell columns 15y (each including a plurality of memory cells 15 disposed in line in the Y direction), and a bit line peripheral circuit 19 including a column decoder and the like. Memory cell 15 stores one-bit information. Each memory cell row 15x configures one entry 2. In response to external designation of memory cell row 15x (entry 2), word line peripheral circuit 17 selects one of word lines 16. All the memory cells 15 connected to selected word line 16 are activated, and data can be read out/written from/to memory cells 15. Bit line peripheral circuit 19 reads out/write data from/to activated memory cells 15 through bit line 18.
Memory region 1 is configured of a plurality of memory cell arrays 14, because configuration of memory region 1 of one memory cell array 14 makes word lines 16 and bit lines 18 longer, resulting in decreased operation speed at reading/writing, and increased power consumption.
x in memory region 1 of FIG. 5 indicates defective memory cell 15. x at A in the figure indicates the case where only one memory cell 15 is defective. In this case, only one bit of one entry 2 becomes defective. x at B in the figure indicates the case where a defect occurs in one word line 16, that is, the case where word line 16 is disconnected, or shorted to a power supply level. In this case, a part or all of the bits of one entry 2 become defective. x at C in the figure shows the case where a defect occurs in one bit line 18, that is, the case where bit line 18 is disconnected or shorted to a power supply level. In this case, all the entries 2 connected to one bit line 18 become defective.
Since the conventional cache memory is configured as described above, all the memory cells 15 configuring memory region 1 must operate normally. Even if one memory cell 15 is defective, the cache memory does not operate normally. Therefore, yield in production of a cache memory of a large capacitance was low.
In order to solve such a problem, a memory circuit is provided for discriminating defective entry 2 including a defective bit, so that defective entry 2 is not used, and that only non-defective entry 2 is used. This is disclosed in Japanese Patent Laying-Open No. 4-175945, and in pages 50 and 51 of ISSCC Digest of Technical Papers 1986. FIG. 8 is a block diagram showing a logical configuration of a cache memory thus improved. The cache memory includes a hardware valid bit region 6 for discriminating defective entry 2 provided in each entry 2. Hardware valid bit region 6 of defective entry 2 including a defective bit shown by x is set to an invalid state ("I" in the figure), and hardware valid bit region 6 of non-defective entry 2 is set to a valid state ("V" in the figure).
Upon external application of address bit train 10, one entry 2 corresponding to index portion 7 included therein is selected. Similar to the case of the cache memory shown in FIG. 5, data, tag data and status valid data are read out from data memory region 3, tag memory region 4, and status valid bit region 5, respectively, of selected entry 2. Hardware valid data is simultaneously read out from hardware valid bit region 6.
When the read hardware valid data is in a valid state, the read tag data and tag portion 11 of address bit train 10 are compared in comparison logic circuit 7. When the tag data and tag portion 11 match, and the read status valid data is in a valid state, hit signal HIT indicating that the read data is desired one is provided outside from comparison logic circuit 7.
When the read hardware valid data is in an invalid state, comparison logic circuit 7 provides outside a signal indicating that the accessed data is invalid. To do so, when the hardware valid data is in an invalid state, miss signal MISS indicating that the read data is invalid may be provided by comparison logic circuit 7 irrespective of the comparison result of the tag data with data portion 11 and the status valid data. The hardware valid data may be provided outside to be subjected to external processing.
FIG. 9 is a circuit diagram of a conventional program circuit 400 actually configuring hardware valid bit region 6. Program circuit 400 includes N channel MOS transistors 22 of the same number as that of entries 2 and program fuses 23 connected in series with transistors 22, and a precharge circuit 25. N channel MOS transistor 22 has its source connected to a ground node, its drain connected to one terminal of program fuse 23, and its gate connected to each entry select line 21. The other terminal of program fuse 23 is connected to the output of precharge circuit 25 through a signal line 24. When entry 2 includes a defective bit, program fuse 23 corresponding to the entry 2 is disconnected. As a result, hardware valid bit region 6 of the entry 2 is set to an invalid state.
Operation will now be described. The potential of signal line 24 is set to a logical high or H level by precharge circuit 25 prior to selection of entry 2. When one entry 2 is selected (when the potential of entry select line 21 attains an H level), N channel MOS transistor 22 for the entry 2 is brought to an on state. When the entry 2 is non-defective, and program fuse 23 for the entry 2 is not disconnected, signal line 24 is conducted to the ground terminal through program fuse 23 and N channel MOS transistor 22, and the potential of signal line 24 attains a logical low or L level. On the other hand, when entry 2 is defective, and program fuse 23 for the entry 2 is disconnected, the potential of signal line 24 is maintained at an H level. Therefore, after selection of entry 2, when the potential of signal line 24 is at an L level, it is determined that entry 2 is in a valid state, and when the potential of signal line 24 is at an H level, it is determined that entry 2 is in an invalid state.
In such a cache memory, when only one memory cell 15 is defective as shown by x at A, and when a defect occurs in one word line as shown by x at B, only one program fuse 23 for entry 2 including the defect may be disconnected. However, when a defect occurs in bit line 18 as shown by x at C, a number of continuous program fuses 23 must be disconnected. Therefore, it took a longer time to disconnect program fuses 23, and it was difficult to reliably disconnect program fuses 23.